OPAC - Pencarian Artikel Jurnal & Majalah Library USD
Menampilkan semua artikel (Halaman 707 dari 34166, Total: 341652 data)
The Long and Winding Road Toward Efficient High-Performance Computing
klik untuk membaca file PDF
| Pengarang | : | William Jalby |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1985-2003 |
| Abstrak | : | The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in finding the best “matches” between advanced hardware capabilities and the software used to program applications, so that top performance will be achieved. Several benchmarks show very disappointing performance progress over the last decade, clearly indicating a mismatch between hardware and software. To remedy this problem, it is important that key performance enablers at the software level-autotuning, performance analysis tools, full application optimization-are understood. For each area, we highlight major limitations and most promising approaches to reaching better performance and energy levels. Finally, we conclude by analyzing hardware and software design, trying to pave the way for more tightly integrated hardware and software codesign. |
Automating the Development of High-Performance Multigrid Solvers
| Pengarang | : | Christian Schmitt |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1969-1984 |
| Abstrak | : | The purpose of a domain-specific language (DSL) is to enable the application programmer to specify a problem, or an abstract algorithm description, in his/her domain of expertise without being burdened by implementation details. The ideal scenario is that the implementation detail is added in an automatic process of program translation and code generation. The approach of domain-specific program generation has lately received increasing attention in the area of computational science and engineering. In this paper, we introduce the new code generation framework Athariac. Its goal is to support the quick implementation of a language processing and program optimization platform for a given DSL based on stepwise term rewriting. We demonstrate the framework's use on our DSL ExaSlang for the specification and optimization of multigrid solvers. On this example, we provide evidence of Athariac's potential for making domain-specific software engineering more productive. |
SPIRAL: Extreme Performance Portability
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1935-1968 |
| Abstrak | : | In this paper, we address the question of how to automatically map computational kernels to highly efficient code for a wide range of computing platforms and establish the correctness of the synthesized code. More specifically, we focus on two fundamental problems that software developers are faced with: performance portability across the ever-changing landscape of parallel platforms and correctness guarantees for sophisticated floating-point code. The problem is approached as follows: We develop a formal framework to capture computational algorithms, computing platforms, and program transformations of interest, using a unifying mathematical formalism we call operator language (OL). Then we cast the problem of synthesizing highly optimized computational kernels for a given machine as a strongly constrained optimization problem that is solved by search and a multistage rewriting system. Since all rewrite steps are semantics preserving, our approach establishes equivalence between the kernel specification and the synthesized program. This approach is implemented in the SPIRAL system, and we demonstrate it with a selection of computational kernels from the signal and image processing domain, software-defined radio, and robotic vehicle control. Our target platforms range from mobile devices, desktops, and server multicore processors to large-scale high-performance and supercomputing systems, and we demonstrate performance comparable to expertly hand-tuned code across kernels and platforms. |
The Sparse Polyhedral Framework: Composing Compiler-Generated Inspector-Executor Code
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1921-1934 |
| Abstrak | : | Irregular applications such as big graph analysis, material simulations, molecular dynamics simulations, and finite element analysis have performance problems due to their use of sparse data structures. Inspector-executor strategies improve sparse computation performance through parallelization and data locality optimizations. An inspector reschedules and reorders data at runtime, and an executor is a transformed version of the original computation that uses the newly reorganized schedules and data structures. Inspector-executor transformations are commonly written in a domain-specific or even application-specific fashion. Significant progress has been made in incorporating such inspector-executor transformations into existing compiler transformation frameworks, thus enabling their use with compile-time transformations. However, composing inspector-executor transformations in a general way has only been done in the context of the Sparse Polyhedral Framework (SPF). Though SPF enables the general composition of such transformations, the resulting inspector and executor performance suffers due to missed specialization opportunities. This paper reviews the history and current state of the art for inspector-executor strategies and reviews how the SPF enables the composition of inspector-executor transformations. Further, it describes a research vision to combine this generality in SPF with specialization to achieve composable and high performance inspectors and executors, producing a powerful compiler framework for sparse matrix computations. |
Domain-Specific Optimization and Generation of High-Performance GPU Code for Stencil Computations
| Pengarang | : | Prashant Singh Rawat |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1902-1920 |
| Abstrak | : | Stencil computations arise in a number of computational domains. They exhibit significant data parallelism and are thus well suited for execution on graphical processing units (GPUs), but can be memory-bandwidth limited unless temporal locality is utilized via tiling. This paper describes how effective tiled code can be generated for GPUs from a domain-specific language (DSL) for stencils. Experimental results demonstrate the benefits of such a domain-specific optimization approach over state-of-the-art general-purpose compiler optimizations. |
Machine Learning in Compiler Optimization
| Pengarang | : | Zheng Wang |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 11) |
| Halaman | : | 1879-1901 |
| Abstrak | : | In the last decade, machine-learning-based compilation has moved from an obscure research niche to a mainstream activity. In this paper, we describe the relationship between machine learning and compiler optimization and introduce the main concepts of features, models, training, and deployment. We then provide a comprehensive survey and provide a road map for the wide variety of different research areas. We conclude with a discussion on open issues in the area and potential research directions. This paper provides both an accessible introduction to the fast moving area of machine-learning-based compilation and a detailed bibliography of its main achievements. |
Setting the Standards for Engineering Education: A History
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1834-1843 |
| Abstrak | : | This month's article reviews the long history of efforts to define a proper standard for engineering education, and the implications this has for the current set of proposed changes to ABET's engineering accreditation criteria. |
Platform Storage Performance With 3D XPoint Technology
| Pengarang | : | Jonathan D. Rosenblatt |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1822-1833 |
| Abstrak | : | With a combination of high performance and nonvolatility, the arrival of 3D XPoint memory promises to fundamentally change the memory-storage hierarchy at the hardware, system software, and application levels. This memory will be deployed first as a block addressable storage device, known as the Intel Optane SSD, and even in this familiar form it will drive basic system change. Access times consistently as fast, or faster, than the rest of the system will blur the line between storage and memory. The low latencies from these solid-state drives (SSDs) allow rethinking even basic storage methodologies to be more memory-like. For example, the manner in which storage performance is measured shifts from inputoutput operations (IOs) at a given queue depth to response time for a given load, like memory is typically measured. System changes to match the low latency of these SSDs are already advanced, and in many cases they enable the application to utilize the SSD's performance. In other cases, additional work is required, particularly on policies set originally with slow storage in mind. On top of these already-capable systems are real applications. System-level tests show that applications such as keyvalue stores and real-time analytics can benefit immediately. These application benefits include significantly faster runtime (up to 3× ) and access to larger data sets than supported in DRAM. Newly viable mechanisms for expanding application memory footprint include native application support or native operating system paging, a significant change in the use of SSDs. The next step in this convergence is 3D XPoint memory accessed through processor load/store operations. Significant operating system support is already in place. The implications of consistently low latency storage and fast persistent memory on computing are great, with applications and systems taking advantage of this new technology as storage as the first to benefit. |
Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1812-1821 |
| Abstrak | : | NAND flash memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology memory device is capable of trading off the performance and endurance with bit density. The more bits per cell there are, the longer latency and shorter lifetime. On the other hand, the performance of such SSDs is limited due to NAND flash access speed as well as the need of garbage collection. Recently, storage class memories (SCMs) like resistive RAM (ReRAM) and phase change RAM (PRAM) have been developed to fill the bandwidth gap between DRAM and NAND flash memory. SCMs are nonvolatile and byte addressable, which are much faster and durable than NAND flash. Therefore, with SCMs, the storage performance would be significantly improved. Hybrid SSDs are promising cost-efficient storage solutions. Various types of memories like single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC) NAND flash memories, and SCMs create lots of opportunities for new system architectures and algorithms. In this paper, the architecture and algorithm design overview of three types of hybrid drives including MLC/TLC NAND flash hybrid, SCM/MLC NAND flash hybrid, and SCM/MLC/TLC NAND flash tri-hybrid are presented. From the evaluation results, hybrid drives demonstrate better performance, endurance, and power consumption, compared to the MLC NAND flash only SSD. Furthermore, the relationship between device reliability and performance of the SCM/NAND flash hybrid SSD has been understood at a system level. There is a tradeoff between acceptable bit error rate of SCM and NAND flash. In addition, the decoding latency of SCM affects the performance of hybrid SSD more than that of NAND flash. |
Phase Change and Magnetic Memories for Solid-State Drive Applications
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1790-1811 |
| Abstrak | : | The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate NAND Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability. |