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Resistive Random Access Memory for Future Information Processing System
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| Pengarang | : | Huaqiang Wu |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1770-1789 |
| Abstrak | : | Resistive random access memory (RRAM) is regarded as one of the most promising emerging memory technologies for next-generation embedded, standalone nonvolatile memory (NVM), and storage class memory (SCM) due to its speed, density, cost, and scalability. Considerable progress has been made in recent years on the manufacturability of RRAM, with low-density RRAM products now in production and the path to higher density parts becoming clearer. This review updates the learning on the fundamental materials and process integration needed for high-volume manufacturing and summarizes very recent progress on array level performance improvement methodology using novel techniques, and circuit level contributions for different applications. The device performance, array integration, and device/circuit codesign for memory systems are discussed. Novel applications besides embedded memory and standalone memory are addressed, including hardware security, neuromorphic computing, and nonvolatile logic systems. |
Reliability of nand-Based SSDs: What Field Studies Tell Us
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1751-1769 |
| Abstrak | : | Solid-state drives (SSDs) based on NAND flash are making deep inroads into data centers as well as the consumer market. In 2016, manufacturers shipped more than 130 million units totaling around 50 Exabytes of storage capacity. As the amount of data stored on solid state drives keeps increasing, it is important to understand the reliability characteristics of these devices. For a long time, our knowledge about flash reliability was derived from controlled experiments in lab environments under synthetic workloads, often using methods for accelerated testing. However, within the last two years, three large-scale field studies have been published that report on the failure behavior of flash devices in production environments subjected to real workloads and operating conditions. The goal of this paper is to provide an overview of what we have learned about flash reliability in production, and where appropriate contrasting it with prior studies performing controlled experiments. |
Reliability of Solid-State Drives Based on NAND Flash Memory
| Pengarang | : | Neal R. Mielke |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1725-1750 |
| Abstrak | : | This paper reviews the reliability of solid-state drives (SSDs) based on NAND Flash memory from the perspectives of failure mechanisms, design mitigations, qualification methods, and field failure rates. NAND reliability is dominated by gradual memory-cell degradation in late life and defects such as interconnect shorts earlier in life. Design mitigations exist for these mechanisms. Qualification methods standardized in JEDEC JESD218 are designed to evaluate the mechanisms and mitigations, over a full drive lifetime, in the laboratory. Full-lifetime qualification provides confidence in the long-term reliability of SSDs that cannot be achieved by the early-life qualifications performed on hard disk drives. If NAND mechanisms are sufficiently suppressed, field reliability will be dominated by non-NAND mechanisms such as firmware bugs, power-loss events, radiation-induced soft errors, and failures in non-NAND components. A wide range of design validation and qualification tests are necessary to evaluate these non-NAND mechanisms. Published field reliability statistics indicate that SSDs are more reliable on average than HDDs, but they are not immune to failure, and there is wide variation among models. The NAND and non-NAND mechanisms are illustrated through new case studies of SSD internal qualification and field reliability data. |
Channel Coding for Nonvolatile Memory Technologies: Theoretical Advances and Practical Considerations
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1705-1724 |
| Abstrak | : | Every bit of information in a storage or memory device is bound by a multitude of performance specifications, and is subject to a variety of reliability impediments. At the other end, the physical processes tamed to remember our bits offer a constant source of risk to their reliability. These include a variety of noise sources, access restrictions, intercell interferences, cell variabilities, and many more issues. Tying together this vector of performance figures with that vector of reliability issues is a rich matrix of emerging coding tools and techniques. Channel coding schemes ensure target reliability and performance and have been at the core of memory systems since their nascent age. In this survey, we first overview the fundamentals of channel coding and summarize well-known codes that have been used in nonvolatile memories (NVMs). Next, we demonstrate why the conventional coding approaches ubiquitously based on symmetric channel models and optimization for the Hamming metric fail to address the needs of modern memories. We then discuss several recently proposed innovative coding schemes. Behind each coding scheme lies an interesting theoretical framework, building on deep ideas from mathematics and the information sciences. We also survey some of the most fascinating bridges between deep theory and storage performance. While the focus of this survey is primarily on the pervasive multilevel NAND Flash, we envision that other benefiting memory technologies will include phase change memory, resistive memories, and others. |
Ultrareliable and Low-Latency Wireless Communication: Tail, Risk, and Scale
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 10) |
| Halaman | : | 1834-1853 |
| Abstrak | : | Ensuring ultrareliable and low-latency communication (URLLC) for 5G wireless networks and beyond is of capital importance and is currently receiving tremendous attention in academia and industry. At its core, URLLC mandates a departure from expected utility-based network design approaches, in which relying on average quantities (e.g., average throughput, average delay, and average response time) is no longer an option but a necessity. Instead, a principled and scalable framework which takes into account delay, reliability, packet size, network architecture and topology (across access, edge, and core), and decision-making under uncertainty is sorely lacking. The overarching goal of this paper is a first step to filling this void. Towards this vision, after providing definitions of latency and reliability, we closely examine various enablers of URLLC and their inherent tradeoffs. Subsequently, we focus our attention on a wide variety of techniques and methodologies pertaining to the requirements of URLLC, as well as their applications through selected use cases. These results provide crisp insights for the design of low-latency and high-reliability wireless networks. |
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives
| Pengarang | : | Leying Guan |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1666-1704 |
| Abstrak | : | NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: 1) effective process technology scaling; and 2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to 1) fewer electrons in the flash memory cell floating gate to represent the data; and 2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including 1) cell-to-cell interference mitigation; 2) optimal multi-level cell sensing; 3) error correction using state-of-the-art algorithms and methods; and 4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future. |
Software Support Inside and Outside Solid-State Devices for High Performance and High Efficiency
| Pengarang | : | Wu, Chengyu,Yang, Jiaqing |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1650-1665 |
| Abstrak | : | In the past decade, flash memory has been in the spotlight across a variety of research communities from circuits to computer systems, and significant progress has been accomplished. This has enabled flash memory to become increasingly pervasive across the entire information technology infrastructure, from consumer electronics to cloud and supercomputing. This paper aims to provide a comprehensive survey on the important advancements and milestones in the domains across flash translation layer (FTL), operating systems, and applications. As the storage device hardware has been quickly commoditized, software becomes increasingly important to tap the potential of flash memory to its full extent. Therefore, a comprehensive survey with a focus on software aspects will be very valuable to the research community and industry. It is our hope that this survey paper will serve as a good reference for system practitioners and researchers. |
Array Architectures for 3D NAND Flash Memories
| Pengarang | : | Rino Micheloni |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1634-1649 |
| Abstrak | : | NAND Flash memories have changed and keep changing our lives. In the past two decades, NAND-based systems, in the form of Flash cards and USB keys, have replaced films and floppy disks. But disruption did not stop there. Today, NAND is really ubiquitous, as it plays the role of storage element inside smartphones and tablets; even further, it is now expanding its reach because solid-state drives (SSDs), i.e., drives built with several NAND devices, are replacing hard disk drives (HDDs) in more and more applications. To fuel this continuous evolution, NAND has to remain very aggressive in terms of cost per bit. When approaching 10-nm technologies, planar NAND is running out of steam: industry and academia have worked hard on finding a solution to this problem for more than a decade. Three-dimensional integration turned out to be the most promising alternative, and it is now eventually reaching the market. This paper is about 3-D NAND Flash memories and the related integration challenges. Charge trap and floating gate 3-D technologies will be discussed with the aid of several bird's-eye views. Advanced layout techniques will thoroughly be analyzed. Finally, future scaling trends will be presented. |
A Survey on MIMO Transmission With Finite Input Signals: Technical Challenges, Advances, and Future Trends
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 106 (No. 10) |
| Halaman | : | 1779-1833 |
| Abstrak | : | Multiple antennas have played an essential role in spatial multiplexing and diversity transmission for a wide range of communication applications. Most advances in the design of high-speed wireless multiple-input-multiple-output (MIMO) systems have been based on information-theoretic principles that demonstrate how to efficiently transmit signals conforming to Gaussian distribution. However, although the Gaussian signal is capacity-achieving, practical systems transmit signals belonging to finite and discrete constellations. Therefore, capacity-achieving transceiver processing based on a Gaussian input signal can be quite suboptimal for practical MIMO systems with discrete constellation input signals. To address this shortcoming, this paper aims to provide a comprehensive overview of MIMO transmission design with finite input signals. It first summarizes existing fundamental results for MIMO systems with finite input signals. Next, focusing on basic point-to-point MIMO systems, it examines transmission schemes based on the three most important criteria for communication systems: mutual-information-driven designs, mean-square-error-driven designs, and diversity-driven designs. In particular, a unified framework is developed for the design of low-complexity transmission schemes applicable to massive MIMO systems in forthcoming 5G wireless networks for the first time. Furthermore, adaptive transmission designs are proposed that switch among these criteria based on channel conditions to formulate the best transmission strategy. A survey is then given of transmission designs with finite input signals for multiuser MIMO scenarios, including MIMO uplink transmission, MIMO downlink transmission, MIMO interference channel, and MIMO wiretap channel. Additionally, transmission designs with finite input signals are discussed for other multi-antenna systems. Finally, a number of technical challenges that remain unresolved at the time of writing are highlighted, and future trends... |
Reviewing the Evolution of the NAND Flash Technology
| Pengarang | : | Emanuel Boputra |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 105 (No. 9) |
| Halaman | : | 1609-1633 |
| Abstrak | : | This paper reviews the recent historical trends of the NAND Flash technology, highlighting the evolution of its main parameters and explaining what allowed it to become not only the most important integrated solution for nonvolatile storage of high volumes of data but also a strong rival eroding the market share of hard-disk drives. The scaling trend followed by planar arrays will be discussed with close attention, along with the major physical constraints impacting the performance and the reliability of modern deca-nanometer technologies. This will make clear why the development of further planar nodes with feature size below ~15 nm, representing today's state of the art, can be considered less favorable than turning all the efforts toward the integration of 3-D arrays. The most promising 3-D architectures will then be reviewed, discussing their benefits and issues and addressing the impact of the change of the integration paradigm from the standpoint of the major NAND applications. |