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Logic Synthesis for Established and Emerging Computing
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| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 165-184 |
| Abstrak | : | Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly-which is computationally possible for instances of limited size today-as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported. |
Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model
| Pengarang | : | Alexander Neckar |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 144-164 |
| Abstrak | : | Braindrop is the first neuromorphic system designed to be programmed at a high level of abstraction. Previous neuromorphic systems were programmed at the neurosynaptic level and required expert knowledge of the hardware to use. In stark contrast, Braindrop's computations are specified as coupled nonlinear dynamical systems and synthesized to the hardware by an automated procedure. This procedure not only leverages Braindrop's fabric of subthreshold analog circuits as dynamic computational primitives but also compensates for their mismatched and temperature-sensitive responses at the network level. Thus, a clean abstraction is presented to the user. Fabricated in a 28-nm FDSOI process, Braindrop integrates 4096 neurons in 0.65 mm2. Two innovations-sparse encoding through analog spatial convolution and weighted spike-rate summation though digital accumulative thinning-cut digital traffic drastically, reducing the energy Braindrop consumes per equivalent synaptic operation to 381 fJ for typical network configurations. |
Efficient Biosignal Processing Using Hyperdimensional Computing: Network Templates for Combined Learning and Classification of ExG Signals
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 123-143 |
| Abstrak | : | Recognizing the very size of the brain's circuits, hyperdimensional (HD) computing can model neural activity patterns with points in a HD space, that is, with HD vectors. Key examined properties of HD computing include: a versatile set of arithmetic operations on HD vectors, generality, scalability, analyzability, one-shot learning, and energy efficiency. These make it a prime candidate for efficient biosignal processing where signals are noisy and nonstationary, training data sets are not huge, individual variability is significant, and energy-efficiency constraints are tight. Purely based on native HD computing operators, we describe a combined method for multiclass learning and classification of various ExG biosignals such as electromyography (EMG), electroencephalography (EEG), and electrocorticography (ECoG). We develop a full set of HD network templates that comprehensively encode body potentials and brain neural activity recorded from different electrodes into a single HD vector without requiring domain expert knowledge or ad hoc electrode selection process. Such encoded HD vector is processed as a single unit for fast one-shot learning, and robust classification. It can be interpreted to identify the most useful features as well. Compared to state-of-the-art counterparts, HD computing enables online, incremental, and fast learning as it demands less than a third as much training data as well as less preprocessing. |
The Next Generation of Deep Learning Hardware: Analog Computing
| Pengarang | : | Wilfried Haensch |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 108-122 |
| Abstrak | : | Initially developed for gaming and 3-D rendering, graphics processing units (GPUs) were recognized to be a good fit to accelerate deep learning training. Its simple mathematical structure can easily be parallelized and can therefore take advantage of GPUs in a natural way. Further progress in compute efficiency for deep learning training can be made by exploiting the more random and approximate nature of deep learning work flows. In the digital space that means to trade off numerical precision for accuracy at the benefit of compute efficiency. It also opens the possibility to revisit analog computing, which is intrinsically noisy, to execute the matrix operations for deep learning in constant time on arrays of nonvolatile memories. To take full advantage of this in-memory compute paradigm, current nonvolatile memory materials are of limited use. A detailed analysis and design guidelines how these materials need to be reengineered for optimal performance in the deep learning space shows a strong deviation from the materials used in memory applications. |
Shannon-Inspired Statistical Computing for the Nanoscale Era
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 90-107 |
| Abstrak | : | Modern day computing systems are based on the von Neumann architecture proposed in 1945 but face dual challenges of: 1) unique data-centric requirements of emerging applications and 2) increased nondeterminism of nanoscale technologies caused by process variations and failures. This paper presents a Shannon-inspired statistical model of computation (statistical computing) that addresses the statistical attributes of both emerging cognitive workloads and nanoscale fabrics within a common framework. Statistical computing is a principled approach to the design of non-von Neumann architectures. It emphasizes the use of information-based metrics; enables the determination of fundamental limits on energy, latency, and accuracy; guides the exploration of statistical design principles for low signal-to-noise ratio (SNR) circuit fabrics and architectures such as deep in-memory architecture (DIMA) and deep in-sensor architecture (DISA); and thereby provides a framework for the design of computing systems that approach the limits of energy efficiency, latency, and accuracy. From its early origins, Shannon-inspired statistical computing has grown into a concrete design framework validated extensively via both theory and laboratory prototypes in both CMOS and beyond. The framework continues to grow at both of these levels, yielding new ways of connecting systems through architectures, circuits, and devices, for the semiconductor roadmap to march into the nanoscale era. |
Computing With Networks of Oscillatory Dynamical Systems
| Pengarang | : | Arijit Raychowdhury |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 73-89 |
| Abstrak | : | As we approach the end of the silicon road map, alternative computing models that can solve at-scale problems in the data-centric world are becoming important. This is accompanied by the realization that binary abstraction and Boolean logic, which have been the foundations of modern computing revolution, fall short of the desired performance and power efficiency. In particular, hard computing problems relevant to pattern matching, image and signal processing, optimizations, and neuromorphic applications require alternative approaches. In this paper, we review recent advances in oscillatory dynamical system-based models of computing and their implementations. We show that simple configurations of oscillators connected using simple electrical circuits can result in interesting phase and frequency dynamics of such coupled oscillatory systems. Such networks can be controlled, programmed, and observed to solve computationally hard problems. Although our discussion in this paper is limited to insulator-to-metal transition devices and spin-torque oscillators, the general philosophy of such a computing paradigm of “let physics do the computing” can be translated to other mediums as well, including micromechanical and optical systems. We present an overview of the mathematical treatments necessary to understand the time evolution of these systems and highlight the recent experimental results in this area that suggest the potential of such computational models. |
DNA Data Storage and Hybrid Molecular–Electronic Computing
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 63-72 |
| Abstrak | : | Moore's law may be slowing, but our ability to manipulate molecules is improving faster than ever. DNA could provide alternative substrates for computing and storage as existing ones approach physical limits. In this paper, we explore the implications of this trend in computer architecture. We present a computer systems perspective on molecular processing and storage, positing a hybrid molecular-electronic architecture that plays to the strengths of both domains. We cover the design and implementation of all stages of the pipeline: encoding, DNA synthesis, system integration with digital microfluidics, DNA sequencing (including emerging technologies such as nanopores), and decoding. We first draw on our experience designing a DNA-based archival storage system, which includes the largest demonstration to date of DNA digital data storage of over three billion nucleotides encoding over 400 MB of data. We then propose a more ambitious hybrid-electronic design that uses a molecular form of near-data processing for massive parallelism. We present a model that demonstrates the feasibility of these systems in the near future. We think the time is ripe to consider molecular storage seriously and explore system designs and architectural implications. |
Leveraging Tactile Internet Cognizance and Operation via IoT and Edge Technologies
| Pengarang | : | Sharief M. A. Oteafy |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 2) |
| Halaman | : | 364-375 |
| Abstrak | : | The Tactile Internet (TI) is building on the premise of remote operation in perceived real-time, and enables a plethora of applications that involve immersive interactions. As we build a future for globalizing skills, delivering haptic feedback across continents, and immersing users in remote environments, we are faced with significant challenges in understanding the context of Tactile Internet interactions, which we refer to as tactile cognizance. The challenge of understanding a remote terminals' context impacts not only the quality and depth of haptic feedback, but our ability to deliver perceived real-time operation. That is, as we develop AI techniques to compensate for the inevitable delay in remote operation, we need more information about a terminal's context and interactions to improve our prediction of movement and feedback. The Internet of Things (IoT) is promising to interconnect billions of sensors, and augment multiple tiers of cognition to expedite and fine-tune sensory acquisition from heterogeneous contexts. In this paper, we will survey recent developments in the IoT, and novel techniques for cloudlet-based cyber foraging (i.e., edge computing) to project how Tactile Internet interactions could benefit from IoT contextualization. We present a taxonomy of edge IoT systems designed for rapid data acquisition, with an emphasis on systems that prioritize stringent reliability and latency mandates. This paper builds on edge computing techniques to propose a framework for multi-tiered cognition in the Tactile Internet to feed its signaling systems, and how future TI codecs could embed contextual information in haptic feedback. |
Softwarization and Network Coding in the Mobile Edge Cloud for the Tactile Internet
| Pengarang | : | - |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 2) |
| Halaman | : | 350-363 |
| Abstrak | : | Future communication systems, such as those enabling the Tactile Internet, will face disruptive changes compared to the state-of-the-art systems, which are 1) highly dynamic topology changes; 2) replacement of the end-to-end paradigm by real mesh topologies; and 3) a massive number of devices. To overcome these disruptive changes, future communication systems will substitute specialized hardware with generic hardware boxes and the softwarization paradigm. Furthermore, this approach will allow for a quick deployment of new services, which was known to the cloud service already. In this paper, we will introduce the most prominent candidates for softwarization such as software-defined networking (SDN) and network function virtualization (NFV) and explain the importance of these technologies for the upcoming 5G communication system and Tactile Internet applications realizing novel mobile edge computing, storage, and networking solutions. Specifically, we will discuss use cases of SDN/NFV such as network coding as a service, and ultrareliable distributed edge caching. Finally, we will describe our holistic testbed at the 5G Lab Germany as a fundamental step toward creating an experiment infrastructure that anticipates the 5G communication systems and Tactile Internet applications. |
Negative Capacitance Transistors
| Pengarang | : | Gunawan |
| Nama Majalah/Jurnal | : | Proceedings of the IEEE |
| Volume / Edisi | : | 107 (No. 1) |
| Halaman | : | 49-62 |
| Abstrak | : | In recent years, the negative capacitance effect in ferroelectric (FE) materials has attracted significant attention from many researchers around the world. The negative capacitance effect promises to reduce the voltage requirement in conventional complementary metal-oxide-semiconductor transistors below what is otherwise believed to be the Boltzmann limit. In this paper, our objective is to discuss the fundamental underpinning of the negative capacitance effect and describe how it can be utilized for transistors. We shall start with a thermodynamic perspective to understand where the reduction in energy dissipation comes from. We then proceed to derive the S curve in an FE material from fundamental principles. The central result of this paper is to associate the negative slope region in the S curve to a physically definable configuration of dipoles in the crystal structure. The design of a negative capacitance transistor is essentially an exercise of stabilizing the FE in the negative slope region of the S curve using the semiconductor capacitance as a series capacitor. |